1. Field of the Invention
The present invention relates to a DA converter circuit for use in a ΔΣ AD modulator, and a ΔΣ AD modulator utilizing the same DA converter circuit, and in particular, to a DA converter circuit for use in a ΔΣ AD modulator which is used in apparatuses such as a communication apparatus, a sensor apparatus, an audio apparatus and the like, and a ΔΣ AD modulator utilizing the same DA converter circuit.
2. Description of the Related Art
A signal processing method as employed in a communication system has been rapidly shifting from an analog system to a digital system. When an AD converter circuit in such a system can be successfully shifted to an analog front end, complicated functions, which were conventionally realized in the analog system, the AD converter circuit can be realized by means of a digital signal processing method so that a level of integration and a performance of the whole system can be improved. In order to realize that, a superior linearity, a large dynamic range, a wide signal band and an image signal eliminating ability may be required for the AD converter circuit.
A ΔΣ AD modulator, which is an AD converter circuit using a ΔΣ modulator, is widely applied not only to sound and instrumentation as in the conventional usage but also to the communication system in order to satisfy the needs resulting from a rapid progress in a higher speed and a wider band. The ΔΣ AD modulator is capable of achieving a high precision using oversampling and noise shaping methods. As an advantageous effect upon using a multi-bit ΔΣ AD modulator to further pursue a higher performance, a higher resolution can be obtained with a lower oversampling ratio (hereinafter referred to as an OSR), and possible problems in the stability can be overcome at the same time (for example, See a first patent document).
Documents related to the present invention are as follows:
(1) Japanese Patent Laid-open Publication No. JP-10-075177-A (referred to as a first non-patent document hereinafter);
(2) S. R. Norsworthy, et al. (editors), “Delta-Sigma Data Converters, —Theory, Design, and Simulation”, IEEE Press, 1997 (referred to as a first patent document hereinafter);
(3) R. Schreier et al., “Speed vs. dynamic range trade-off in oversampling data converters”, C. Toumazou et al. (editors), Trade-Offs in Analog Circuit Design, The Designer's Companion, Kiuwer Academic Publishers, pp. 631, 644 and 645, 2002 (referred to as a second patent document hereinafter);
(4) Y. Geerts al., “Design of Multi-bit Delta-Sigma A/D Converters”, Kluwer Academic Publishers, 2002 (referred to as a third patent document hereinafter);
(5) A. Yasuda et al., “A third-order Δ-Σ modulator using second-order noise-shaping dynamic element matching”, IEEE Journal of Solid-State Circuits, Vol. 33, pp. 1876–1886, December 1998 (referred to as a fourth patent document hereinafter);
(6) H. San et al., “An element rotation algorithm for multi-bit DAC nonlinearities in complex bandpass delta-sigma AD modulators”, IEEE 17th International Conference on VLSI Design, Mumbai, India, pp. 151–156, January 2004 (referred to as a fifth patent document hereinafter); and
(7) H. San et al., “A Noise-Shaping Algorithm of Multi-bit DAC Nonlinearities in Complex Bandpass ΔΣ AD modulators”, IEICE Transactions on Fundamentals, Vol. E87-A, No. 4, pp 792–800 April 2004 (referred to as a sixth patent document hereinafter).
However, in contrast to a one-bit DA converter having a superior linearity, a non-linearity of an internal DA converter of the multi-bit ΔΣ AD modulator is not noise-shaped in the modulator, and this leads to disadvantageous deterioration in the precision of the entire AD converter.
FIG. 1A is a block diagram showing a configuration of a low-pass ΔΣ AD modulator according to a prior art. FIG. 1B is an equivalent circuit diagram of the low-pass ΔΣ AD modulator shown in FIG. 1A.
Referring to FIG. 1A, the low-pass ΔΣ AD modulator includes a subtracter SU1, a low-pass filter LP1, an AD converter AD1, and a DA converter DA1. An analog input signal Ain is inputted to the subtracter SU1. The subtracter SU1 subtracts a feedback signal, which is outputted from the DA converter DA1, from the inputted analog input signal Ain, and then, outputs a signal having the subtraction result to the AD converter AD1 via the low-pass filter LP1 having a predetermined low-pass characteristic. The AD converter AD1 converts the inputted signal into a digital output signal Dout, and outputs the same digital output signal Dout, which is further outputted to the DA converter DA1. Further, the DA converter DA1 DA-converts the inputted digital output signal Dout into an analog signal, and feeds it back to the subtracter SU1.
In the block diagram of the equivalent circuit of FIG. 1B, X (z) corresponds to the analog input signal Ain, while Y(z) corresponds to the digital output signal Dout. The low-pass filter LP1 has a transfer function H (z). In the AD converter AD1, a quantization noise E (z) is added to an adder SM1. In a DA converter SM2, a non-linearity error δ(z) is added to an adder SM2. In FIG. 1B, M (z) denotes an output signal from the DA converter DA1.
In this case, a relationship between the input signal X (z) and the output signal Y(z) in the low-pass ΔΣ AD modulator of FIG. 1 is represented by the following equation.
                              Y          ⁡                      (            z            )                          =                                                            H                ⁡                                  (                  z                  )                                                            1                +                                  H                  ⁡                                      (                    z                    )                                                                        ⁡                          [                                                X                  ⁡                                      (                    z                    )                                                  -                                  δ                  ⁡                                      (                    z                    )                                                              ]                                +                                    1                              1                +                                  H                  ⁡                                      (                    z                    )                                                                        ⁢                          E              ⁡                              (                z                )                                                                        (        1        )            
As clearly shown in the foregoing equation (1)-the quantization noise E (z) of the internal AD converter AD1 is noise-shaped, while the non-linearity error δ(z) of the DA converter is directly outputted without any noise-shaping process, and this obviously makes it difficult to realize the ΔΣ AD modulator with a higher precision. Therefore, in order to noise-shape the non-linearity of the internal DA converter of the multi-bit ΔΣ AD modulator, there was proposed a DWA (Data Weighted Averaging; this means averaging data with weighting) algorithm, in which a digital signal processing circuit is provided at the previous stage of the internal DA converter DA1 so that a dynamic element matching is performed (for example, see the second to sixth non-patent document).
Next, a DA converter of segment switched capacitor type and mismatch of its capacitances will be described below.
FIG. 2A is a circuit diagram showing a configuration of the switched capacitor DA converter of segment type according to the prior art. FIG. 2B is a circuit diagram showing an electrically charging operation of the switched capacitor DA converter of segment type shown in FIG. 2A. FIG. 2C is a circuit diagram showing an electrically discharging operation of the DA converter of segment switched capacitor type shown in FIG. 2A.
The DA converter of segment switched capacitor type having a resolution of nine levels shown in FIG. 2A includes the followings:
(a) eight unit capacitors C0 to C7 as connected in parallel to each other;
(b) an operational amplifier OPA having a feedback capacitor Cref;
(c) an electrically charging switch SW11 for supplying a predetermined reference voltage Vref to the respective unit capacitors C0 to C7, respectively;
(d) an electrically discharging switch SW12 for electrically discharging the electric charges stored in the respective unit capacitors C0 to C7 to the operational amplifier OPA; and
(e) switches SW0 to SW7 for supplying the reference voltage Vref to the unit capacitors C0 to C7 or grounding the same unit capacitors C0 to C7.
It would be ideal for capacitance values of all of the unit capacitors Ck to be equal to each other, however, the capacitance values are actually different from designed values due to variation in a manufacturing process of an IC chip. The capacitance values are represented by the following equation:Ck≡C+ek (k=0, 1, 2, . . . , 7)  (2),where C≡(C0+C1+C2+ . . . +C7)/8  (3), ande0+e1+e2+ . . . +e7=0  (4).
A symbol ek in the foregoing equation denotes a mismatch value of the capacitance value Ck which is a deviation value from an average capacitance C. As shown in FIG. 2B, when the digital input signal is “m”, the electrically charging switch SW11 is turned on, while the switch SW12 is turned off. Further, a number “m” of switches SW0 to SWm−1 are switched over to a contact “a” side thereof so that the unit capacitors C0, C1, C2, . . . , Cm−1 are connected to the reference voltage Vref. On the other hand, only a number “7−m+1” of other switches SWm to SW7 are switched over to a contact “b” side thereof so that the unit capacitors Cm, Cm+1, . . . , C7 are grounded. In this case, the unit capacitors C0, C1, C2, . . . , Cm−1 are supplied with electric charges. Next, after a predetermined time interval, the electrically charging switch SW11 is turned off, while the switch SW12 is turned on, and all of the switches SW0 to SW7 are switched over to the contact “a” side thereof so that the electric charges as stored in the unit capacitors C0, C1, C2, . . . , Cm−1 are discharged to the operational amplifier OPA, as shown in FIG. 2C. At that time, an output voltage Vout of the DA converter of segment switched capacitor type is represented by the following equation:
                              V          out                =                                            -              m                        ⁢                                                  ⁢                          C                              C                ref                                      ⁢                          V              ref                                +                      δ            .                                              (        5        )            
A non-linearity δ of the foregoing DA converter is obtained by the following equation:
                    δ        ≡                              -                                                            e                  0                                +                                  e                  1                                +                                  e                  2                                +                …                +                                  e                                      m                    -                    1                                                                              C                ref                                              ⁢                                    V              ref                        .                                              (        6        )            
As is apparent from the foregoing equation (3), an output power spectrum of the AD converter based on mismatch values e0, e1, . . . , e7 (which equivalently correspond to the non-linearity δ of the DA converter DA1) is evenly shown in a signal band.
Next, a first-order low-pass DWA algorithm will be described below. FIG. 3A is a block diagram showing a DA converter circuit when the DA converter DA1 according to the prior art is subjected to a first-order noise shape based on a first-order DWA algorithm. FIG. 3B is an equivalent circuit diagram of the DA converter circuit shown in FIG. 3A.
Referring to FIG. 3A, a digital low-pass filter LP11 having the transfer function of(1/(1−z−1)) is inserted at the previous stage of the DA converter DA1 having the non-linearity δ(z), and an analogue high-pass filter HP11 having the transfer function of (1−z−1) is inserted at the next stage of the DA converter DA1. A relationship among a digital input signal A1, non-linearity δ(z) of the DA converter DA1 and analog output signal A4 is represented by the following equation:A4(z)=A1(z)+(1−z−1)δ(z)  (7).
As shown in FIG. 3A, the low-pass filter LP11 of FIG. 3A includes an adder SM11, and a delay circuit DL11 for delaying an output signal from the adder SM11 by a predetermined clock cycle and thereafter feeding back the same delayed output signal to the adder SM11. As is apparent from FIG. 3, the non-linearity δ(z) of the DA converter DA1 is subjected to the first-order noise shape by the high-pass filter HP11 having the transfer function of (1−z−1). As shown in FIG. 3B, the high-pass filter HP11 of FIG. 3A includes a subtracter SU11 and a delay circuit DL21 for delaying a signal inputted to the subtracter SU11 by a predetermined clock cycle and thereafter inputting the delayed signal to the subtracter SU11.
However, it is not possible in reality to realize the circuit described above. For example, when a digital input signal A1 (n) is always an integer 2, an input signal A2 (n) to the DA converter DA1 is infinite in accordance with the increase of a timing “n”, leading the DA converter DA1 to exceed its input range, as a result of which the DA conversion becomes impossible. In order to deal with the situation, the first-order DWA algorithm capable of equivalently realizing the circuit of FIG. 3 was proposed (for example, See the second patent document)-the first-order DWA algorithm will be described below.
The followings are assumed for the DA converter of segment switched capacitor type.
(A) Respective capacity cells CSm (m=0, 1, 2, . . . , 7) of the DA converter of segment switched capacitor type are arranged in a ring shape as shown in FIG. 4. Each of the capacity cells CSm includes a capacitor Cm and a switch SWm for connecting the capacitor Cm to a ring connecting line RR. Further, the ring connecting line RR is connected to the reference voltage source Vref via the electrically charging switch SW11 and also connected to a non-inversion input terminal of the operational amplifier OPA having the feedback capacitor Cref.
(B) A pointer for memorizing a position of the capacity cell as turned on is provided in the DA converter. An indicated value of the pointer at a timing “n” is P (n), and at a timing “n+1”, the P (n)-th capacity cell is selected in accordance with inputted data, and then, it is turned on. Based on the foregoing configuration, the following operation is carried out.
(C) It is assumed that the input data signal is A1 (n)=αn (n=0, 1, 2, 3, . . . ) at the timing “n”.
(D) Respective switches of a number αn of capacity cells CS (mod8 (P (n)+1)), CS (mod8 (P (n)+2)), CS (mod8 (P (n)+3)), . . . , CS (mod8 (P (n)+αn)) are turned on so that they are connected to the reference voltage source Vref of FIG. 2B. In the present specification, in place of a general notation “x modulo y” or “x mod y” which represents a remainder as obtained when x is divided by y, a simplified notation “modyz” is used for the description.
(E) The indicated value of the pointer at the timing “n+1” is set to P (n+1)=mod8 (P (n)+αn). As described, when the capacity cell whose switch is turned on is selected, the mismatch value of the capacity cell (that is the non-linearity δ(z) of the DA converter DA1) is subjected to the first-order noise shape.
By the way, the ΔΣ AD converter included such problems that power consumption of the AD converter was relatively large and a chip area unfavorably increased due to its higher OSR. In order to solve the problems, they have paid attention to transformation of the ΔΣ AD modulator into the multi-bit configuration to reduce the OSR. However, the multi-bit DA converter includes a non-linearity resulting from the matching precision of the apparatus as described earlier, and this may unfavorably cause an adverse influence on the performance of the entire AD converter. In particular, the foregoing problem is even worse when fine processing is adopted to promote downsizing and high speed.
In order to overcome such problems, the low-pass element rotation method utilizing the first-order noise shaping was proposed as described above, however, the method can only exert a limited effect in obtaining a higher signal to noise ratio (SNR). On the other hand, the second-order noise shaping method has been proposed, however, it is not suitable for practical use because a required circuit configuration is too complicated.